This invention relates to the architecture of digital devices on a semiconductor chip which store and process digital signals. These devices include, for example, digital microprocessors and digital controllers for various equipment.
Two such digital devices of the prior art are illustrated in FIGS. 1 and 2. The FIG. 1 device performs its functional operations in a serial fashion; whereas the FIG. 2 device performs its functional operations in a parallel fashion. Thus, the FIG. 1 device has a simpler architecture, but is slower in operation, than the FIG. 2 device.
Suppose, for example, that one function which those devices were to perform is to receive digital operands from input registers IR1 and IR2, to add those operands together, to store that sum in output register OR1, to shift that sum by one bit position to the right, and to store the shifted sum in output register OR2. This operation takes four cycle times to perform in the FIG. 1 device; whereas it takes only two cycle times to perform in the FIG. 2 device.
During the first cycle time in the FIG. 1 device, data in register 10 is transferred through multiplexor 11 and shifter 12 (which is controlled to shift zero bit positions) into a RAM 13. Next, data from input register 14 is sent through multiplexor 11 to arithmetic logic unit 15; the previously stored data in RAM 13 is also sent to arithmetic logic unit 15; and the sum is stored in RAM 13. Next, the sum in RAM 13 is sent to shifter 12 and to output register 16; and the shifted sum from shifter 12 is stored back in RAM 13. Then, the shifted sum in RAM 13 is sent through multiplexor 11 to output register 17.
By comparison, in the FIG. 2 device, the same operation is performed as follows. During the first cycle, data in input registers 20 and 24 are sent through respective multiplexors 21b and 21c to arithmetic logic unit 25; and the sum is then sent through multiplexors 21a and 21e respectively to RAM 23 and output register 26. Then in the next cycle, the stored sum in RAM 23 is sent through multiplexor 21d to shifter 22, and the shifted sum is sent through multiplexor 21e to output register 27.
The speed at which the FIG. 2 device performs its operations is, of course, an attractive feature. However, to obtain that speed, it is necessary that each multiplexor 21a-21e be sent separate control signals on respective leads 28a-28e from a control memory 29. Since each multiplexor 21a-21e has six inputs, at least three encoded digital signals must be sent to each of the multiplexors on the respective control leads.
Thus, control memory 29 which stores these control signals must be relatively wide in comparison to control memory 19 of the FIG. 1 device. That FIG. 1 device has only one multiplexor 11, and it requires only two encoded digital control signals on leads 18 to select its inputs. This, of course, is also an attractive feature because a relatively narrow control memory requires less chip space for its implementation.
Accordingly, a primary object of the invention is to provide a new and improved architecture for a digital device on a semiconductor chip which allows data to be processed quickly in various parallel paths in response to a relatively narrow control word.